1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to a semiconductor circuit device having a hierarchical power supply structure according to an SCRC (subthreshold leakage current reduced control) technique.
2. Description of the Prior Art
A semiconductor circuit device having a hierarchical power supply structure is provided with a main power supply line and a sub power supply line, with a P-channel MOS transistor connected therebetween. The semiconductor circuit device is further provided with a main ground line and a sub ground line, with an N-channel MOS transistor connected therebetween. A logic circuit such as an invertor outputting a logical high-level signal in a standby state is connected between the main power supply line and the sub ground line, while a logic circuit such as an invertor outputting a logical low-level signal in the standby state is connected between the sub power supply line and the main ground line.
In an active state, both the P- and N-channel MOS transistors are turned on and hence the voltage of the sub power supply line reaches a power supply voltage identically to the main power supply line, while the voltage of the sub ground line reaches a ground voltage identically to the main ground line. Therefore, the aforementioned logic circuit outputs a high- or low-level signal in response to an input signal as general.
In the standby state, on the other hand, both the P- and N-channel MOS transistors are turned off and hence no power supply voltage is supplied to the sub power supply line and no ground voltage is supplied to the sub ground line. While the logic circuit connected to the main power supply line can normally output a high-level signal, a subthreshold current flowing in this logic circuit is reduced since the sub ground line is disconnected from the main ground line. While the logic circuit connected to the main ground line can normally output a low-level signal, a subthreshold leakage current flowing in this logic circuit is also reduced since the sub power supply line is disconnected from the main power supply line.
In the standby state, however, the sub power supply line and the sub ground line are disconnected from the main power supply line and the main ground line respectively and hence the voltage of the sub power supply line lowers to increase the potential difference between the main power supply line and the sub power supply line. Further, the voltage of the sub ground line increases to also increase the potential difference between the main ground line and the sub ground line. When the semiconductor circuit device shifts from the standby state to the active state and the sub power supply line is shorted to the main power supply line, therefore, it takes time for the voltage of the sub power supply line to reach the power supply voltage. Further, it also takes time for the voltage of the sub ground line to reach the ground voltage when the sub ground line is shorted to the main ground line. Consequently, the operating speed of the logic circuit is disadvantageously slowed down.
In order to solve this problem, U.S. Pat. No. 5,659,517 discloses a voltage set circuit for setting a sub power supply line at a reference voltage Vref1 while setting a sub ground line at a reference voltage Vref2. While this voltage set circuit can prevent a voltage drop of the sub power supply line and a voltage rise of the sub ground line in a standby state, a subthreshold leakage current flowing in a logic circuit disadvantageously increases. In other words, no sufficient effect of reducing the subthreshold leakage current can be attained by disconnecting the sub power supply line and the sub ground line from a main power supply line and a main ground line respectively.
U.S. Pat. No. 5,724,297 discloses a transistor for temporarily shorting a sub power supply line and a sub ground line when an internal circuit shifts from an active state to a standby state, in order to reduce current consumption. However, this gazette discloses no means for charging the sub power supply line and the sub ground line.
An object of the present invention is to provide a semiconductor circuit device which can prevent a voltage drop of a sub power supply line and a voltage rise of a sub ground line when shifting from a standby state to an active state while keeping an effect of reducing a subthreshold leakage current thereby preventing a logic circuit from an operation delay.
Another object of the present invention is to provide a semiconductor circuit device reducing power consumption.
According to an aspect of the present invention, a semiconductor circuit device having an active state and a standby state comprises a main power supply line, a sub power supply line, a first switching element, a main ground line, a sub ground line, a second switching element, a first logic circuit, a second logic circuit, a first constant current circuit and a second constant current circuit. The main power supply line receives a power supply voltage. The first switching element is connected between the main power supply line and the sub power supply line, turned on in the active state and turned off in the standby state. The main ground line receives a ground voltage. The second switching element is connected between the main ground line and the sub ground line, turned on in the active state and turned off in the standby state. The first logic circuit is connected between the main power supply line and the sub ground line, and outputs a logical high level in the standby state. The second logic circuit is connected between the sub power supply line and the main ground line, and outputs a logical low level in the standby state. The first constant current circuit supplies a constant current to the sub power supply line. The second constant current circuit supplies a constant current to the sub ground line.
In this semiconductor circuit device, the sub power supply line is supplied with the constant current, whereby the voltage thereof does not remarkably drop below the power supply voltage even in the standby state. Further, this current is so constant that a subthreshold leakage current flowing in the second logic circuit does not increase beyond necessity. The sub ground line is also supplied with the constant current, whereby the voltage thereof does not remarkably rise from the ground voltage. Further, this current is also constant and hence a subthreshold leakage current flowing in the first logic circuit does not increase beyond necessity. Consequently, the semiconductor circuit device can be prevented from a delay of the operating speed in an initial stage of the active state while suppressing increase of current consumption.
Preferably, the first constant current circuit includes a first charge circuit, a first monitor circuit and a first control circuit. The first charge circuit charges the sub power supply line. The first monitor circuit monitors a current supplied from the first charge circuit to the sub power supply line. The first control circuit so controls the first charge circuit as to keep the current monitored by the first monitor circuit constant. The second constant current circuit includes a second charge circuit, a second monitor circuit and a second control circuit. The second charge circuit charges the sub ground line. The second monitor circuit monitors a current supplied from the second charge circuit to the sub ground line. The second control circuit so controls the second charge circuit as to keep the current monitored by the second monitor circuit constant.
More preferably, the first monitor circuit includes a first resistance element inserted into the main ground line. The first control circuit includes a first differential amplifier receiving a voltage developed across the first resistance element and having an offset voltage. The first charge circuit includes a first transistor having a gate receiving an output voltage of the first differential amplifier. The second monitor circuit includes a second resistance element inserted into the main power supply line. The second control circuit includes a second differential amplifier receiving a voltage developed across the second resistance element and having an offset voltage. The second charge circuit includes a second transistor having a gate receiving an output voltage of the second differential amplifier.
Alternatively, the first monitor circuit includes a first resistance element inserted into the sub power supply line. The first control circuit includes a first differential amplifier receiving a voltage developed across the first resistance element and having an offset voltage. The first charge circuit includes a first transistor having a gate receiving an output voltage of the first differential amplifier. The second monitor circuit includes a second resistance element inserted into the sub ground line. The second control circuit includes a second differential amplifier receiving a voltage developed across the second resistance element and having an offset voltage. The second charge circuit includes a second transistor having a gate receiving an output voltage of the second differential amplifier.
In this semiconductor circuit device, the first resistance element monitors the current flowing from the sub power supply line to the main ground line and the charge of the sub power supply line is so controlled that this current is constant. Consequently, the charge current for the sub power supply line can be regularly kept constant. Further, the second resistance element monitors the current flowing from the main power supply line to the sub ground line, and the charge of the sub ground line is so controlled that this current is constant. Consequently, the charge current for the sub ground line can be regularly kept constant.
Preferably, the semiconductor circuit device further comprises a short circuit for shorting the sub power supply line and the sub ground line in the standby state.
In the aforementioned semiconductor circuit device, the sub power supply line is shorted to the sub ground line in the standby state, whereby the discharge current for the sub power supply line is utilized as the charge current for the sub ground line. Consequently, current consumption can be reduced.
According to another aspect of the present invention, a semiconductor circuit device having an active state and a standby state comprises a main power supply line, a sub power supply line, a switching P-channel MOS transistor, a main ground line, a sub ground line, a switching N-channel MOS transistor, a first logic circuit, a second logic circuit, a first back gate voltage supply circuit and a second back gate voltage supply circuit. The main power supply line receives a power supply voltage. The switching P-channel MOS transistor is connected between the main power supply line and the sub power supply line, turned on in the active state and turned off in the standby state. The main ground line receives a ground voltage. The switching N-channel MOS transistor is connected between the main ground line and the sub ground line, turned on in the active state and turned off in the standby state. The first logic circuit is connected between the main power supply line and the sub ground line, and outputs a logical high level in the standby state. The second logic circuit is connected between the sub power supply line and the main ground line, and outputs a logical low level in the standby state. The first back gate voltage supply circuit supplies the power supply voltage to a back gate of the switching P-channel MOS transistor in the active state, while supplying a voltage higher than the power supply voltage to the back gate of the switching P-channel MOS transistor in the standby state. The second back gate voltage supply circuit supplies the ground voltage to a back gate of the switching N-channel MOS transistor in the active state, while supplying a voltage lower than the ground voltage to the back gate of the switching N-channel MOS transistor.
In the aforementioned semiconductor circuit device, the power supply voltage is supplied to the back gate of the P-channel MOS transistor and the ground voltage is supplied to the back gate of the N-channel MOS transistor in the active state, whereby a substrate effect is reduced and the operating speeds of these transistors are increased as a result. In the standby state, on the other hand, the voltage higher than the power supply voltage is supplied to the back gate of the P-channel MOS transistor and the voltage lower than the ground voltage is supplied to the back gate of the N-channel MOS transistor, whereby the substrate effect is increased and subthreshold leakage currents of these transistors are reduced as a result.
According to still another aspect of the present invention, a semiconductor circuit device includes a first hierarchical block and a plurality of second hierarchical blocks. The first hierarchical block includes a first power supply system, a first receiving circuit and a plurality of first transmission circuits. The first power supply system supplies a prescribed voltage to an internal circuit in the first hierarchical block. The first receiving circuit receives an externally supplied first request signal and activates the first power supply system. The plurality of first transmission circuits are disposed in correspondence to the plurality of second hierarchical blocks respectively. Each of the first transmission circuits transmits a second request signal to the second hierarchical block corresponding thereto. Each of the second hierarchical blocks includes a second power supply line and a second receiving circuit. The second power supply system supplies a prescribed voltage to an internal circuit in the second hierarchical block. The second receiving circuit receives a second request signal and activates the second power supply system.
In the aforementioned semiconductor circuit device, the first power supply system is activated in response to the externally supplied first request signal, and then the second power supply system is activated in response to the second request signal from the first hierarchical block. Consequently, no unnecessary power supply system is activated but power consumption can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.